• Perform Netlist-to-GDS design flow, including floorplanning, placement,timing, optimization, clock tree systhesis and routing.
• Support STA timing analysis and fixing
• Perform physical verification, including DRC, LVS, IR drop and DFM analysis.

• From 3 years work experience
• Major EE/CS
• Familiar with Cadence Innovus or Synopsys ICC2/Fusion Complier
• English communication (prefer candidate with TOEIC 730-855 or relevant)
• Experience in 65/40/28nm IC design experiences is a plus

BENEFITS:

• Competitive annual salary package: performance bonus, 13-month salary, salary annual increase
• Insurance full salary
• PVI Premium Health care package applied for employee since Probation
• PVI Premium Health care package applied for Family members after Probation
• Free motorbike parking
• Monthly meal & transportation allowances
• Annual health check
• Company trip, voucher/gifts on Birthday & Special occasions.
• Dynamic enviroment with talented people